1. Field of the Invention
The present invention relates to the field of computers. More specifically, the present invention relates to computer architecture.
2. Description of the Related Art
Instructions are generally stored in a memory hierarchy that includes an instruction cache to help satisfy instruction bandwidth requirements of modern high-performance processors. To execute the instructions, processors typically fetch a line of the instruction cache. Each cache line includes a group of instructions. If the execution path of a sequence of instructions is linear, a sequential set of cache lines will supply the processor with appropriate instructions for execution. However, if a branch type instruction is encountered, the execution path may diverge and require the processor to fetch instructions corresponding to a non-sequential cache line. Hence, the cache line of instructions to fetch next is not precisely known until execution trajectory from the current fetch group of instructions is known.
Advanced high-performance microprocessors often prefetch cache lines in an attempt to improve the likelihood that a later needed instruction can be fetched from cache. In general, prefetch is performed without precise information regarding execution trajectory and, as pipeline depths increase and/or speculative execution increases, prefetch can consume substantial memory bandwidth. Fetching of sequential cache lines comports with at least one potential execution path, which is linear. However, the occurrence of a branch type instruction introduces the possibility that instructions of the next cache line are not within an application's execution path. Accordingly, processors may forgo or cancel prefetching of a next cache line of instructions if a presumed execution path through instructions of a preceding cache line includes a branch type instruction, particularly if such a branch is predicted taken. Typically, forbearance or cancellation is designed to avoid the squandering of memory bandwidth. Unfortunately, the occurrence of a branch type instruction, even a predicted-taken branch, is not necessarily determinative that instructions within the next cache line, or even subsequent instructions of the preceding cache line, are not within an application's execution path.
Forgoing or canceling a prefetch of the next cache line would be undesirable if the next cache line were, in fact, in the execution path. However, extraneous prefetching inevitably consumes precious memory bandwidth. Accordingly, techniques are desired that efficiently characterize branch targets and intelligently prefetch instructions based on the characterization.